With a surge in consumption of data across different platforms, there has been a rise in demand for devices that support reliable data transfer rates while maintaining the integrity and noise margin for the data and associated communication channels. The integrity of data is further pronounced in specific digital circuits that utilizes precise clock signals to time operations of different components to generate a coherent output that retains the integrity and meaning of data without any loss in quality and data rates. Examples of such digital circuits may include a PS converter, an M: N multiplexer, a data flip flop, a latch, a clock divider circuit, and the like. Such digital circuits may be further utilized as inbuilt embedded components of wireless transmitters, CPU buses, processor circuitries, modems, and the like.
Conventional digital circuits (such as PS converters, flip flops, latches, multiplexers, etc.) process data with an error rate in the outputted data that is detected by a receiver component that receives the output of the conventional digital circuits. The receiver component may track low frequency (LF) jitter whilst high frequency (HF) jitter may pass, untracked, through the receiver component and thereby cause a reduction in a jitter tolerance of the receiver component. Jitter tolerance is a measure of the receiver component's ability to tolerate HF jitter at a reliable error rate. Different sources of HF jitter may be present in the digital circuit, arising from both external and internal sources. External sources may include jitter from an applied clock or data source. Internal sources may arise from normal component variations and limitations. One such internal jitter source may be inter-symbol interference (ISI). The effect of ISI is significantly pronounced in the output data rate of the conventional digital circuits. ISI is usually caused by a superposition of successive bits when each bit transition has not been completed within a single bit period, which may be verified by an examination of eye diagram for a continuous portion of bits from the output data. The ISI may be caused by particular circuit components that are repeated within the digital circuit, such as a tri-state gate.
Conventionally, a tri-state circuit act as a switch that is time synchronized to operate a transistor-based network in a pull-up configuration and a pull-down configuration, in accordance with a rising or a falling edge of input clock signal. Each transistor in the pull-up configuration or the pull-down configuration may have intrinsic capacitance, such as a self-loading capacitance. A maximum output current may be utilized to charge or discharge such intrinsic capacitance, which may further define a response time of charging/discharging for the intrinsic capacitance. Conventional tri-state gate utilizes multiple transistors, for example, 3, 4, or even 8 transistors in a series configuration to realize the functional performance of the tri-state gate. Thus, the effective intrinsic capacitance may increase by a factor equal to the number of transistors in series. Accordingly, a response time to charge/discharge the effective intrinsic capacitance may proportionally increase with the increase in the intrinsic capacitance and a decrease in the maximum output current. ISI may be caused in cases where, the charge/discharge time and response time increases to a value that may be substantially larger than a duration of a bit at the output of the tri-state circuit.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one skill in the art, through comparison of described systems with some aspects of the present disclosure, as set forth in the remainder of the present application and with reference to the drawings.